Regviz

Freescale Semiconductor /MK60DZ10 /SDHC /IRQSIGEN

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Interpret as IRQSIGEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CCIEN 0 (0)TCIEN 0 (0)BGEIEN 0 (0)DINTIEN 0 (0)BWRIEN 0 (0)BRRIEN 0 (0)CINSIEN 0 (0)CRMIEN 0 (0)CINTIEN 0 (0)CTOEIEN 0 (0)CCEIEN 0 (0)CEBEIEN 0 (0)CIEIEN 0 (0)DTOEIEN 0 (0)DCEIEN 0 (0)DEBEIEN 0 (0)AC12EIEN 0 (0)DMAEIEN

CEBEIEN=0, CCEIEN=0, BGEIEN=0, TCIEN=0, CTOEIEN=0, CINTIEN=0, DINTIEN=0, CIEIEN=0, CINSIEN=0, DTOEIEN=0, DEBEIEN=0, DCEIEN=0, BWRIEN=0, CCIEN=0, CRMIEN=0, BRRIEN=0, DMAEIEN=0, AC12EIEN=0

Description

Interrupt Signal Enable Register

Fields

CCIEN

Command Complete Interrupt Enable

0 (0): Masked

1 (1): Enabled
TCIEN

Transfer Complete Interrupt Enable

0 (0): Masked

1 (1): Enabled
BGEIEN

Block Gap Event Interrupt Enable

0 (0): Masked

1 (1): Enabled
DINTIEN

DMA Interrupt Enable

0 (0): Masked

1 (1): Enabled
BWRIEN

Buffer Write Ready Interrupt Enable

0 (0): Masked

1 (1): Enabled
BRRIEN

Buffer Read Ready Interrupt Enable

0 (0): Masked

1 (1): Enabled
CINSIEN

Card Insertion Interrupt Enable

0 (0): Masked

1 (1): Enabled
CRMIEN

Card Removal Interrupt Enable

0 (0): Masked

1 (1): Enabled
CINTIEN

Card Interrupt Enable

0 (0): Masked

1 (1): Enabled
CTOEIEN

Command Timeout Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
CCEIEN

Command CRC Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
CEBEIEN

Command End Bit Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
CIEIEN

Command Index Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
DTOEIEN

Data Timeout Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
DCEIEN

Data CRC Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
DEBEIEN

Data End Bit Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
AC12EIEN

Auto CMD12 Error Interrupt Enable

0 (0): Masked

1 (1): Enabled
DMAEIEN

DMA Error Interrupt Enable

0 (0): Masked

1 (1): Enabled

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data